This invention relates to a correlation detecting circuit for use in an adaptive equalizer system and, more particularly, to a correlation detecting circuit for use in an adaptive equalizer system for a digital radio transmission system.
In general, an adaptive equalizer system of the type described is supplied through a transmission path with a received signal subjected to modulation at a modulation rate. The received signal carries a transmission data sequence digitized by a reference clock signal. The reference clock signal has a reference clock frequency which is equal to the modulation rate. The modulation may be, for example, quadrature amplitude modulation (QAM). The received signal has a waveform subject to a distortion which results from degradation of a characteristic in the transmission path and interruption in the transmission path. The adaptive equalizer system serves to equalize the distortion of the waveform, as well known in the art.
An adaptive equalizer system is disclosed in U.S. Pat. No. 4,453,256 issued to T. Ryu and assigned to the instant assignee. According to Ryu, the adaptive equalizer system comprises a transversal filter for filtering the received signal into an equalized signal in response to a plurality of controllable tap gains and a demodulator for demodulating the equalized signal into a reproduced clock signal, a reproduced data sequence, and a digital error signal. The reproduced clock signal is a reproduction of the reference clock signal. The reproduced data sequence is a reproduction of the transmission data sequence. The digital error signal is related to the reproduced data sequence. The adaptive equalizer system further comprises a gain control circuit responsive to the reproduced clock signal, to the reproduced data sequence, and to the digital error signal for controlling the controllable tap gains by the use of an equalizing algorithm. The equalizing algorithm is, for example, a zero forcing (ZF) algorithm. The gain control circuit comprises a correlation detecting circuit and an integrating circuit.
The correlation detecting circuit comprises a delaying circuit and an Exclusive logic circuit. The delaying circuit is for delaying the reproduced data sequence and the digital error signal to produce a delayed data sequence and a delayed error signal in synchronism with the reproduced clock signal. The delaying circuit comprises a plurality of flip flops. The delayed data sequence, the delayed error signal, the reproduced data sequence, and the digital error signal are supplied to the Exclusive logic circuit as a plurality of input signals. The Exclusive logic circuit is for carrying out an exclusive logic operation on the input signals to produce a plurality of correlation signals which represent cross-correlation between the reproduced data sequence and the digital error signal. The Exclusive logic circuit comprises a plurality of exclusive logic gates. Each of the exclusive logic gates is either an Exclusive OR gate or an Exclusive NOR gate. The integrating circuit is for integrating the correlation signals to produce a plurality of integrated signals as the controllable tap gains.
In general, a conventional correlation detecting circuit is implemented either as an integrated circuit (IC) or a large-scale integrated circuit (LSI). Each of the IC and LSI comprises a plurality of complementary metal oxide semiconductor (CMOS) circuits. This is because each CMOS circuit has a low power consumption. However, the CMOS circuit has a maximum CMOS operation speed which is about thirty-five in terms of megahertz and is lower than that of other circuits, for example, a current mode logic (CML) circuit. Therefore, the conventional correlation detecting circuit can not be used in the adaptive equalizer system supplied with the received signal of the modulation rate which is higher than the maximum CMOS operation speed if the conventional correlation detecting circuit comprises the CMOS circuits. Inasmuch as the adaptive equalizer system is, for example, for four-by-four quadrature amplitude modulation, namely, 16-QAM, and is supplied with the received signal of a bit transfer rate which is equal to two hundreds megabits per second, the modulation rate is equal to fifty megahertz and is higher than the maximum CMOS operation speed. In this case, the conventional correlation detecting circuit must be composed of discrete integrated circuits, each of which comprises a plurality of CML circuits. As a result, the conventional correlation detecting circuit is disadvantageous in that it is impossible to render the conventional correlation detecting circuit compact and that it is impossible to have a low power consumption.